The present invention relates to multi-queue storage devices generally and, more particularly, to a circuit and method for supporting multicast/broadcast operations in multi-queue storage devices.
Communication devices may use storage devices to store information that is transferred between devices operating at different speeds. Such communication devices may provide multicast and broadcast functions.
Referring to FIG. 1, a block diagram of a conventional communications device 10 is shown. The communications device 10 comprises a port 12 and a switch fabric 14. The port 12 comprises a packet storage device 15, a packet classifier 16, a queue manager 18 and a scheduler 20. A number of management buses 22a-22n transfer management information between the packet classifier 16, the queue manager 18 and the scheduler 20. A number of data buses 23a-23n transfer data between the packet classifier 16, the queue manager 18 and the packet storage device 15. The management bus 22n is generally required to connect the packet classifier 16 to the scheduler 20.
The present invention concerns a circuit comprising a memory and a control circuit. The memory may be configured to (i) hold one or more packets of information and (ii) send the held packets of information in response to one or more control signals. The control circuit may be configured to generate the one or more control signals.
The objects, features and advantages of the present invention include providing a device that may (i) provide multicast operations, (ii) broadcast operations and/or (iii) independent multicast/broadcast operations.